Abstract
Most of market-available logic analyzers are designed for hardware debug purposes and cannot record continuous measurement in long-term while in different fields of scientific research it is necessary to make data acquisition within small periods (less then 1 ms) during several hours or even days. The common example is real-time communication worst-case jitter analysis. This paper introduces an easy to implement approach how to create a logic analyzer for such kind of task on a basis of a low-cost Field-Programmable Gate Array (FPGA) kit and a personal computer. The Author provides both sample FPGA design files compatible with an open-source toolchain and the approach how to collect data using standard software and Octave scripts to post-process the experimental result. Following the Author's guidelines even with minimal knowledge in FPGA design makes it easy to modify the introduced hardware for specific laboratory team needs.