Abstract
The emergence of the AI era driven by Large Language Models (LLMs) and the next-generation high-definition multimedia interface for immersive technologies (AR/VR/metaverse) have created an unprecedented demand for high-bandwidth interconnects. While optical communication systems provide a broad bandwidth, their relatively low power efficiency continues to limit their deployment in new applications. This work addresses the power efficiency challenges in CMOS optical transceiver design, leveraging the inherent cost and integration advantages of CMOS technology. After outlining the design principles for low-power optical transmitter (Tx) and receiver (Rx) design, we present a comprehensive design of a low-power optical transceiver chipset implemented in 28 nm CMOS. The Tx features a high-impedance asymmetric current-steering output stage with a stacked architecture that facilitates unipolar power supply operation for the efficient anode driving of a common-cathode VCSEL array and achieved a power efficiency of 1.59 pJ/bit. The Rx incorporates a tail-current-controlled Cherry-Hooper-based variable gain amplifier (VGA), which achieved a transimpedance gain that ranged from 68.4 to 78.5 dBΩ and a power efficiency of 1.06 pJ/bit. The Rx-Tx back-to-back measurements confirmed successful data transmission at 4 × 20 Gbps, which demonstrated an overall power efficiency of 2.65 pJ/bit.