Abstract
Josephson superconducting qubits and parametric amplifiers are prominent examples of superconducting quantum circuits that have shown rapid progress in recent years. As such devices become more complex, the requirements for reproducibility of their electrical properties across a chip are being tightened. Critical current of the Josephson junction Ic is the essential electrical parameter in a chip. So, its variation is to be minimized. According to the Ambegaokar-Baratoff formula, critical current is related to normal-state resistance, which can be measured at room temperature. In this study, we focused on the dominant source of non-uniformity for the Josephson junction critical current-junction area variation. We optimized Josephson junction fabrication process and demonstrated resistance variation of 9.8-4.4% and 4.8-2.3% across 22 × 22 mm(2) and 5 × 10 mm(2) chip areas, respectively. For a wide range of junction areas from 0.008 to 0.12 μm(2), we ensure a small linewidth standard deviation of 4 nm measured over 4500 junctions with linear dimensions from 80 to 680 nm. We found that the dominate source of junction area variation limiting [Formula: see text] reproducibility is the imperfection of the evaporation system. The developed fabrication process was tested on superconducting highly coherent transmon qubits (T1 > 100 μs) and a nonlinear asymmetric inductive element parametric amplifier.