Abstract
This paper was focused on logic gates, D-latch, parallel-parallel shift-registers, and parallel-series shift registers, which are used as basic circuits in numerous circuits as well as computational and comparative units. To design proposed shift registers, D-latch which is the vital gate, is designed carefully for minimum size, decreasing number of cells and good performance for delay. The proposed level-sensitive parallel-in parallel-out (PIPO) shift registers with reset terminal and with both set and reset terminals (single-layer and multi-layer), edge-sensitive PIPO shift registers with reset and set/reset abilities (single-layer and multi-layer), and the parallel-in serial-out (PISO) shift registers were designed using the proposed D-latches. Simulations show that the proposed level-sensitive PIPO shift-register set and reset terminals has 145 QCA cells, 0.13 μm(2) occupied area, and delay of about 1.25 cycles of QCA clock. In addition, the proposed edge-sensitive PIPO shift-register circuit with set-and-reset pins has 163 QCA cells, 0.17 μm(2) occupied area, and delay of about 1.25 cycles of QCA clocks. All designs and simulation results were made in the QCADesigner software.