Abstract
A new design for high density integration greater than gigabits of perpendicular-magnetic-tunnel-junction (p-MTJ) spin-valve, called the double pinned (i.e., bottom and top pinned structures) p-MTJ spin-valve achieved a multi-level memory-cell operation exhibiting four-level resistances. Three key magnetic properties, the anisotropy exchange field (H(ex)) of the bottom pinned structure, the coercivity (H(c)) of the double free-layer, and the H(c) of the top pinned structure mainly determined four-level resistances producing tunneling-magnetoresistance (TMR) ratios of 152.6%, 33.6%, and 166.5%. The three key-design concepts are: i) the bottom pinned structure with a sufficiently large H(ex) to avoid a write-error, ii) the H(c) of the double free-layer (i.e., ~0.1 kOe) much less than the H(c) of the top pinned structure (i.e., ~1.0 kOe), and iii) the top pinned structure providing different electron spin directions.