Current transformer (CT) saturation classification using empirical mode decomposition (EMD) and relevance vector machine (RVM)

基于经验模态分解(EMD)和相关向量机(RVM)的电流互感器(CT)饱和分类

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Abstract

The fault is taking place in the power system where the saturation of the Current Transformer (CT) is occurring, among other variations of system parameters. Empirical Mode Decomposition (EMD) and Relevance Vector Machine (RVM) detection of Current Transformer (CT) saturation has been found to be a reliable, data-based method of protecting the power system. In this approach, a power system is modelled in PSCAD, with faults being added at various points, fault resistances and fault origin angles to provide a high volume of secondary CT current signals under saturated and unsaturated conditions. The simulated data contains realistic nonlinearities such as partial and severe saturation effects that normally arise after fault commencement. The CT current signals obtained are passed through EMD, which breaks down the nonlinear waveform into a collection of Intrinsic Mode Functions (IMFs). These IMFs bring about concealed oscillatory elements connected to signal distortion as a result of saturation. Empirical properties are obtained from the IMFs, like the energy distribution, instant frequency changes, kurtosis, skewness, and entropy. These characteristics are very sensitive to distortion of the waveforms, and thus are the appropriate signals to show saturation in CT. EMD with RVM technique are proven using MATLAB software as a means of ensuring successful classification of the CT saturation phenomenon. The features are extracted and represent the input to a Relevance Vector Machine (RVM) classifier that is trained on the labelled data to be able to distinguish between saturated and unsaturated cases. The proposed EMD-RVM scheme detects CT saturation within 23.5 ms, making it suitable for fast relay operation. The extracted EMD features provide clear separability between normal and saturated conditions, enabling accurate classification through RVM. A hardware-in-the-loop setup is also prepared for future real-time validation and deployment. SUPPLEMENTARY INFORMATION: The online version contains supplementary material available at 10.1038/s41598-026-35444-2.

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