Abstract
In perovskite solar cells (PSCs), the charge carrier recombination obstacles mainly occur at the ETL/perovskite and HTL/perovskite interfaces, which play a decisive role in the solar cell performance. Therefore, this study aims to enhance the flexible PSC (FPSC) efficiency by adding the newly designed CBz-PAI-interlayer (simply CBz-PAI-IL) at the perovskite/HTL interface. In addition, substantial work has been carried out on five different HTLs (Se/Te-Cu(2)O, CuGaO(2), V(2)O(5,) and CuSCN, including conventional Spiro-OMeTAD as a reference HTL with and without CBz-PAI-IL), using drift-diffusion simulation to find suitable FPSC design to attain the maximum PCE. Interestingly, PET/ITO/AZO/ZnO NWs/FACsPbBrI(3)/CBz-PAI/Se/Te-Cu(2)O/Au device architecture demonstrates the highest achievable power conversion efficiency (PCE) of 27.9 %. The findings of this study confirmed that the reference device (without IL) displays a large valence band edge (VBE)/highest occupied molecular orbital (HOMO) energy level misalignment compared to the modified interface device (with CBz-PAI-IL that reduces VBE/HOMO level mismatch) that eases the hole transport, simultaneously, it reduces the charge carrier recombinations at the interface, resulting in diminished V(oc) losses in the device. Furthermore, the influence of perovskite absorber thickness and defect density, parasitic resistances, and working temperature are systematically examined to govern the superior FPSC efficiency and concurrently understand the device physics.