Analysis and design of diode physical limit bandwidth efficient rectification circuit for maximum flat efficiency, wide impedance, and efficiency bandwidths

分析和设计二极管物理极限带宽高效整流电路,以实现最大平坦效率、宽阻抗和高效带宽

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Abstract

Generally, a conventional voltage doubler circuit possesses a large variation of its input impedance over the bandwidth, which results in limited bandwidth and low RF-dc conversion efficiency. A basic aspect for designing wideband voltage doubler rectifiers is the use of complex matching circuits to achieve decade and octave impedance and RF-dc conversion efficiency bandwidths. Still, the reported techniques till now have been accompanied by a large fluctuation of the RF-dc conversion efficiency over the operating bandwidth. In this paper, we propose a novel rectification circuit with minimal inter-stage matching that consists of a single short-circuit stub and a virtual battery, which contributes negligible losses and overcomes these existing problems. Consequently, the proposed rectifier circuit achieves a diode physical-limit-bandwidth efficient rectification. In other words, the rectification bandwidth, as well as the peak efficiency, are controlled by the length of the stub and the physical limitation of the diodes.

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