Abstract
The continuous scaling down of MOSFETs is one of the present trends in semiconductor devices to increase device performance. Nevertheless, with scaling down beyond 22 nm technology, the performance of even the newer nanodevices with multi-gate architecture declines with an increase in short channel effects (SCEs). Consequently, to facilitate further increases in the drain current, the use of strained silicon technology provides a better solution. Thus, the development of a novel Gate-All-Around Field-Effect Transistor (GAAFET) incorporating a strained silicon channel with a 10 nm gate length is initiated and discussed. In this device, strain is incorporated in the channel, where a strained silicon germanium layer is wedged between two strained silicon layers. The GAAFET device has four gates that surround the channel to provide improved control of the gate over the strained channel region and also reduce the short channel effects in the devices. The electrical properties, such as the on current, off current, threshold voltage (V(TH)), subthreshold slope, drain-induced barrier lowering (DIBL), and I(on)/I(off) current ratio, of the 10 nm channel length GAAFET are compared with the 22 nm strained silicon channel GAAFET, the existing SOI FinFET device on 10 nm gate length, and IRDS 2022 specifications device. The developed 10 nm channel length GAAFET, having an ultrathin strained silicon channel, delivers enriched device performance, being augmented in contrast to the IRDS 2022 specifications device, showing improved characteristics along with amended SCEs.