Abstract
The mechanical reliability of glass substrates is a key challenge for their adoption in advanced semiconductor packaging. This study employs finite element analysis to systematically evaluate the risk of edge crack propagation in large glass panels during redistribution layer (RDL) fabrication. The influence of critical factors-including crack location, number of RDLs, glass material and thickness, dielectric ABF properties, Cu content, and edge clearance-was examined. Results revealed that top-edge crack near the RDL/glass interface pose the highest failure risk due to elevated peeling stress and increased energy release rate (ERR). The risk of propagation intensifies with more RDLs and thinner glass, while high CTE (coefficients of thermal expansion) glasses such as D263, Gorilla, and ceramic glass markedly suppress crack growth compared with borofloat 33 and fused silica. Among ABF dielectrics, GZ-41 demonstrated superior crack resistance owing to its low CTE and moderate stiffness. Although higher Cu content slightly reduced ERR, its effect remained limited. Edge clearance strongly affects reliability, with ≥300 µm providing effective suppression of crack propagation. These findings provide quantitative design guidelines for glass interposer structures, emphasizing the optimization of dielectric material selection, glass substrate and thickness, and layout constraints such as edge clearance. The proposed methodology and results will contribute to establishing reliable strategies for deploying ultra-thin glass panels in advanced semiconductor packaging.