Abstract
Image segmentation implementation provides simplified and effective feature information of image. Neural network algorithms have made significant progress in the application of image segmentation task. However, few studies focus on the implementation of hardware circuits with high-efficiency analog calculations and parallel operations for image segmentation problem. In this paper, a memristor-based competitive Hopfield neural network circuit is proposed to deal with the image segmentation problem. In this circuit, the memristive cross array is applied to store synaptic weights and perform matrix operations. The competition module based on the Winner-take-all mechanism is composed of the competition neurons and the competition control circuit, which simplifies the energy function of the Hopfield neural network and realizes the output function. Operational amplifiers and ABM modules are used to integrate operations and process external input information, respectively. Based on these designs, the circuit can automatically implement iteration and update of data. A series of PSPICE simulations are designed to verify the image segmentation capability of this circuit. Comparative experimental results and analysis show that this circuit has effective improvements both in processing speed and segmentation accuracy compared with other methods. Moreover, the proposed circuit shows good robustness to noise and memristive variation.