Abstract
In this work, an innovative design model aimed at enhancing the efficacy of ground-state probabilistic logic with a binary energy landscape (GSPL-BEL) is presented. This model enables the direct conversion of conventional CMOS-based logic circuits into corresponding probabilistic graphical representations based on a given truth table. Compared to the conventional approach of solving the configuration of Ising model-basic probabilistic gates through linear programming, our model directly provides configuration parameters with embedded many-body interactions. For larger-scale probabilistic logic circuits, the GSPL-BEL model can fully utilize the dimensions of many-body interactions, achieving minimal node overhead while ensuring the simplest binary energy landscape and circumventing additional logic synthesis steps. To validate its effectiveness, hardware implementations of probabilistic logic gates were conducted. Probabilistic bits were introduced as Ising cells, and cascaded conventional XNOR gates along with passive resistor networks were precisely designed to realize many-body interactions. HSPICE circuit simulation results demonstrate that the probabilistic logic circuits designed based on this model can successfully operate in free, forward, and reverse modes, exhibiting the simplest binary probability distributions. For a 2-bit × 2-bit integer factorizer involving many-body interactions, compared to the logic synthesis approach, the GSPL-BEL model significantly reduces the number of consumed nodes, the solution space (in the free-run mode), and the number of energy levels from 12, 4096, and 9-8, 256, and 2, respectively. Our findings demonstrate the significant potential of the GSPL-BEL model in optimizing the structure and performance of probabilistic logic circuits, offering a new robust tool for the design and implementation of future probabilistic computing systems.