Abstract
In real-time digital signal processing, the multirate transformation is a commonly used technique for interpolation and decimation. Comb-based decimation filters are used in wireless applications because of their minimal complexity and effective alias suppression. One symmetrical Finite Impulse Response (FIR) filter that may be used as a decimation filter is the cascaded integrator-comb (CIC) filter. Compared to other decimation filters, the CIC filter operates faster and uses less hardware because it does not require multipliers. Efficient digital filtering is critical in modern wireless communication systems, where real-time processing and resource optimization are essential. This paper presents a multi-stage hybrid polyphase CIC filter architecture implemented on a Xilinx Virtex-4 Field-Programmable Gate Array (FPGA) to enhance signal processing performance. The proposed method integrates a polyphase CIC filter with an FIR compensation filter, addressing the passband droop and improving frequency response. By leveraging polyphase decomposition and pipeline optimization, the design reduces computational complexity while maintaining high accuracy. The FPGA-based implementation ensures low latency, high throughput, and efficient hardware utilization, making it ideal for high-speed wireless applications. Experimental results demonstrate that the proposed filter achieves superior filtering performance compared to conventional CIC filters, offering a robust solution for real-time digital signal processing. The proposed method achieves substantial hardware savings, utilizing only 289 Slice Registers, 25 LUTs, 346 Flip-Flops, 63 BRAMs, and 76 DSPs, compared to the highest values from prior works, which consumed up to 628 Registers, 442 LUTs, 654 BRAMs, and 364 DSPs. This represents a reduction of up to 54% in Slice Registers, 94% in LUTs, and 88% in DSPs, highlighting the efficiency of the proposed architecture for SDR-based IoT gateways.