A low switching loss GaN trench MOSFET design utilizing a triple-shield structure

一种采用三层屏蔽结构的低开关损耗GaN沟槽MOSFET设计

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Abstract

An innovative GaN trench MOSFET featuring an ultra-low gate-drain charge (Q(gd)) is proposed, with its operational mechanisms thoroughly investigated using TCAD simulations. This novel MOSFET design introduces a triple-shield structure (BPSG-MOS) comprising three critical components: (1) a grounded split gate (SG), (2) a P+ shield region (PSR), and (3) a semi-wrapped BP layer that extends the P-shield beneath the gate and along the sidewalls of the trench gate. Both the SG and PSR effectively reduce gate-drain coupling, transforming most of the gate-drain capacitance (C(gd)) into a series combination of gate-source capacitance (C(gs)) and drain-source capacitance (C(ds)). Furthermore, the BP layer refines the gate-drain capacitance by converting the C(gd) at the trench gate sidewalls into C(gs). This configuration significantly lowers C(gd), resulting in an ultra-low Q(gd). Compared to the dual-shield MOSFET (PSGT-MOS) and the conventional trench MOSFET (TG-MOS), the BPSG-MOS achieves reductions in C(gd) by 81% and 98%, respectively.

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