Abstract
As processor performance advances, the cache has become an essential component of computer architecture. Moreover, the rapid digital transformation of daily life has resulted in electronic devices storing greater amounts of sensitive information. Thus, device users are becoming more concerned about the security of their personal information, so improving processor performance is no longer the sole priority. Hardware vulnerabilities are generally more difficult to detect and address compared to software viruses and related threats. A common technique for exploiting hardware vulnerabilities is through side-channel attacks. They can bypass software security to extract personal information directly from hardware components like the cache or registers. This paper introduces a novel architecture for the arithmetic logic unit (ALU) and associated memory controller (MC) based on the RISC-V microarchitecture to mitigate side-channel attacks. The proposed approach employs hardware-generated random numbers and has minimal design costs, negligible impact on the original system structure, seamless integration, and easy modification of internal components. Results are presented that show it is effective against side-channel attacks.