Abstract
With the evolving modern-day communication applications, there is a need for an effectively improved performance in multiplication operations. In today's scenario, multiplication operations based on Vedic mathematics have the primary advantage that the propagation delay due to a larger number of input bits is reduced compared to other multipliers. Higher speed Vedic multipliers, especially based on Urdhva Tiryagbhyam (vertically and crosswise) sutra, perform multiplication in a way that allows parallel processing with reduced delay. Compared to conventional multipliers like array or Booth multipliers, Vedic multipliers may have less area and power, depending on implementation. In this work, a high-speed 64-bit reversible Vedic multiplier is proposed using five different adders, namely reversible ripple carry adder (RRCA), reversible carry look-ahead adder (RCLA), reversible carry save adder (RCSA), reversible carry bypass or carry skip adder (RCSKA)adder, and reversible carry select adder (RCSLA). The main objective of utilizing logic optimization in reversible logic along with the Vedic multiplier is to develop low-power and high-speed digital circuits. The proposed n-bit reversible Vedic multiplier is simulated using Xilinx Vivado 2019.1 and synthesized in the Cadence EDA tool in 90 nm and 180 nm technology. The proposed 16-bit reversible Vedic multipliers using the proposed 2-bit reversible multiplier provide 24% and 28% less propagation delay than the related work Mohana Priya et al. (Int. J. Syst. Assur. Eng. Manag. 14:829-835, 2023). The 16-bit reversible Vedic multiplier proposed using the existing 2-bit reversible multiplier provides 53% lesser area and 52% less power than the reference work Deepa et al. (Sadhana 44:197, 2019). Similarly, the proposed 32-bit reversible Vedic multiplier offers 15% better delay than (Padma et al. in Comput. Electr. Eng. 92:107178, 2021), 53% less area, and 45% less power than (Deepa et al.in Sadhana 44:197, 2019). Using the proposed reversible Vedic multiplier, a 32-bit MAC unit is designed and implemented using Cadence 90 nm and 180 nm technology. Thus, the proposed work can be applied to the most promising fields such as Microprocessors to design MAC units, to find the convolution in Digital signal processing applications, Communication, RF sensing applications, etc.