Abstract
This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO(2) interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔV(th) and ΔV(FN) variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔV(th) and ΔV(FN), while HTRB showed only a 4% variation in both ΔV(th) and ΔV(FN). The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.