Abstract
As the feature size of integrated circuits has been scaled down to 10 nm, the rapid increase in the electrical resistance of copper (Cu) metallization has become a critical issue. To alleviate the resistance increases of Cu lines, co-sputtered CoW and CoB alloying metals were investigated as conductors and barriers in this study. Annealing CoM (M = W or B)/SiO(2)/p-Si structures reduced the resistivity of CoM alloys, removed sputtering-deposition-induced damage, and promoted adhesion. Additionally, both annealed CoW/SiO(2) or CoB/SiO(2) structures displayed a negligible V(fb) shift from capacitance-voltage measurements under electrical stress, revealing an effective barrier capacity, which is attributed to the formation of MO(x) layers at the CoM/SiO(2) interface. Based on the thermodynamics, the B(2)O(3) layer tends to form more easily than the WO(x) layer. Hence, the annealed CoB/SiO(2)/p-Si MIS capacitor had a higher capacitance and a larger breakdown strength did than the annealed CoW/SiO(2)/p-Si MIS capacitor.