Abstract
Vertical architectures for organic electrochemical transistors (OECTs), due to their submicrometer channel lengths, have presented themselves as a straightforward design approach for achieving high g(m)/τ ratios, a figure of merit that assesses the performance of the devices by virtue of their transconductance (g(m) = dI(D)/dV(GS)) and switching time constant (τ). However, as the practical limitations of the geometries are overcome, the influence of parasitic phenomena becomes more dominant and limits the performance of the device. One approach to reduce the detrimental effects of parasitic resistance in the drain-source circuit is to use a four-point sourcing technique. Here, vertical OECTs are fabricated with four-point structures to approach the intrinsic limit of these devices. It is shown that this approach improves the saturation behavior of the devices, closing the gap between measured g(m) and intrinsic transconductance g(mi) at their peak values. Overall, the results discussed here provide insight into the effects of parasitic resistance on OECTs, which in contrast to field-effect transistors, are not as extensively documented.