日期:
2020 年 — 2026 年
2020
2021
2022
2023
2024
2025
2026
影响因子:

68-channel neural signal processing system-on-chip with integrated feature extraction, compression, and hardware accelerators for neuroprosthetics in 22 nm FDSOI

采用 22 纳米 FDSOI 工艺的 68 通道神经信号处理片上系统,集成了特征提取、压缩和硬件加速器,适用于神经假体。

Guo, Liyuan; Weiße, Annika; Zeinolabedin, Seyed Mohammad Ali; Schüffny, Franz Marcus; Stolba, Marco; Ma, Qier; Wang, Zhuo; Scholze, Stefan; Dixius, Andreas; Berthel, Marc; Partzsch, Johannes; Walter, Dennis; Ellguth, Georg; Höppner, Sebastian; George, Richard; Mayr, Christian

Plasticity and Adaptation in Neuromorphic Biohybrid Systems

神经形态生物混合系统中的可塑性和适应性

George, Richard; Chiappalone, Michela; Giugliano, Michele; Levi, Timothée; Vassanelli, Stefano; Partzsch, Johannes; Mayr, Christian

Two Homologous Enzymes of the GalU Family in Rhodococcus opacus 1CP-RoGalU1 and RoGalU2

混色红球菌 1CP 中 GalU 家族的两种同源酶-RoGalU1 和 RoGalU2

Kumpf, Antje; Partzsch, Anett; Pollender, André; Bento, Isabel; Tischler, Dirk

A Biohybrid Setup for Coupling Biological and Neuromorphic Neural Networks

用于耦合生物神经网络和神经形态神经网络的生物混合装置

Keren, Hanna; Partzsch, Johannes; Marom, Shimon; Mayr, Christian G

Memory-Efficient Deep Learning on a SpiNNaker 2 Prototype

在 SpiNNaker 2 原型上实现内存高效的深度学习

Liu, Chen; Bellec, Guillaume; Vogginger, Bernhard; Kappel, David; Partzsch, Johannes; Neumärker, Felix; Höppner, Sebastian; Maass, Wolfgang; Furber, Steve B; Legenstein, Robert; Mayr, Christian G

Reducing the computational footprint for real-time BCPNN learning

降低实时 BCPNN 学习的计算量

Vogginger, Bernhard; Schüffny, René; Lansner, Anders; Cederström, Love; Partzsch, Johannes; Höppner, Sebastian

Network-driven design principles for neuromorphic systems

神经形态系统的网络驱动设计原则

Partzsch, Johannes; Schüffny, Rene

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

利用28nm CMOS工艺的开关电容实现突触前短期可塑性和停止学习突触

Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

Configurable analog-digital conversion using the neural engineering framework

基于神经工程框架的可配置模数转换

Mayr, Christian G; Partzsch, Johannes; Noack, Marko; Schüffny, Rene

VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality

基于VLSI的2.8 Gevent/s数据包AER接口实现,具有路由和事件排序功能

Scholze, Stefan; Schiefer, Stefan; Partzsch, Johannes; Hartmann, Stephan; Mayr, Christian Georg; Höppner, Sebastian; Eisenreich, Holger; Henker, Stephan; Vogginger, Bernhard; Schüffny, Rene