Abstract
Hafnium oxide-based ferroelectrics, particularly zirconium-doped HfO(2) (HZO), have demonstrated excellent compatibility with CMOS fabrication processes. However, the impact of post-metallization annealing (PMA)-a key step in optimizing device performance-on CMOS and FeFET co-integrated devices has yet to be fully explored. This study investigates the effects of PMA under N(2) and H(2) ambients on the electrical properties of pMOSFET and nFeFET devices monolithically co-integrated on an 8-inch wafer. N(2) annealing leads to a significantly larger memory window in FeFETs, attributed to enhanced crystallinity and reduced oxide-trapped charges. In contrast, while H(2) annealing is less effective in improving ferroelectric properties, it markedly lowers the interface trap density (D(it)) in both CMOS and FeFET devices. This reduction in D(it) leads to improved SS, as reflected in the higher gain observed in FeFET-based co-integrated inverters. These findings offer valuable insights for optimizing PMA conditions based on the performance requirements for co-integrated FeFET and CMOS devices.