Abstract
2D semiconductors are promising channel materials for next-generation thin-film transistors (TFTs) in Internet of Things (IoT) devices. However, their inert, dangling-bond-free surfaces make uniform high-k dielectric integration challenging and can lead to interface defect formation. Here, a scalable inter-dielectric engineering strategy is introduced to address this challenge, using initiated chemical vapor deposition (iCVD) to deposit an ultrathin nonpolar poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3) film as an interlayer between MoS(2) and HfO(2). This pV3D3 buffer layer forms uniformly without pinholes or clusters on MoS(2), yielding excellent interface quality and effectively suppressing HfO(2)-induced uncontrollable doping effect and trap formation in MoS(2). As a result, the MoS(2) top-gate transistors with pV3D3/HfO(2) dielectric exhibit nearly ideal switching characteristics, including a subthreshold swing (SS) of 60.9 mV dec(-1), negligible hysteresis of ≈20 mV, and low interface trap density (D(it,avg)) of 8.9 × 10(10) cm(-2 )e(-1 )V(-1). Furthermore, an overlapping top-gate structure design minimizes contact resistance, achieving an I(ON)/I(OFF) ratio above 10(8), a field-effect mobility (µ(FE)) of 19.2 cm(2 )V(-1 )s(-1), and minimum subthreshold swing (SS(min)) of 80.6 mV dec(-1). This iCVD based inter-dielectric method is further validated on a flexible MoS(2) top-gate transistors and logic circuits, demonstrating its potential for scalable and large-area high-performance 2D electronics.