Accurate FPGA-Based Velocity Measurement with an Incremental Encoder by a Fast Generalized Divisionless MT-Type Algorithm

基于FPGA的增量编码器快速通用无分割MT型算法的精确速度测量

阅读:1

Abstract

Velocity measurement by an incremental encoder is an important issue for advanced motion control applications such as robotics. In this paper, we deal with a kind of MT-type velocity estimation method. Though the conventional MT method is well known and has been well proven in practice, it requires execution of an arithmetic division operation that prevents an efficient implementation on low-cost FPGA-based control platforms. Thus, we propose a divisionless MT-type algorithm, which can provide a similar performance in velocity estimation accuracy as the conventional method, but requiring significantly less FPGA resources, since it implements only simple arithmetic operations such as addition, subtraction, and multiplication, that can be implemented more easily on the processing hardware. Furthermore, the algorithm is fast in execution, thus, it provides the output in only a few clock cycles. Though the proposed algorithm can be described in a recursive form, the stability of the estimation process is not jeopardized, although it is an important issue in this case. Hence, the algorithm is introduced in a form which assures stability in a wide speed range. We show the implementation of the algorithm on the experimental FPGA platform. The experimental results validated the proposed divisionless MT-type algorithm fully for accurate velocity estimation.

特别声明

1、本页面内容包含部分的内容是基于公开信息的合理引用;引用内容仅为补充信息,不代表本站立场。

2、若认为本页面引用内容涉及侵权,请及时与本站联系,我们将第一时间处理。

3、其他媒体/个人如需使用本页面原创内容,需注明“来源:[生知库]”并获得授权;使用引用内容的,需自行联系原作者获得许可。

4、投稿及合作请联系:info@biocloudy.com。